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| INTEGRATED CIRCUITS DATA SHEET TDA8006 Multiprotocol IC Card coupler Product specification Supersedes data of 2000 Feb 21 File under Integrated Circuits, IC02 2000 Oct 30 Philips Semiconductors Product specification Multiprotocol IC Card coupler FEATURES * 80C52 core with 16 kbyte ROM and 256 byte RAM * Extra 1 kbyte RAM outside the core for data storage * Control and communication through a standard RS232 full duplex interface or a parallel interface * Specific ISO 7816 UART with parallel access on I/O for automatic convention processing, variable baud rate through frequency or division ratio programming, error management at character level for T = 0, extra guard time register * VCC generation (5 V 5% or 3 V 5%, 65 mA maximum with controlled rise and fall times) * Card clock generation (up to 10 MHz) with two times synchronous frequency doubling * Card clock STOP HIGH, clock STOP LOW or 1.25 MHz (from internal oscillator) for card power-down mode * CLKOUT output for clocking external devices with either fxtal, 12fxtal or 14fxtal * Automatic activation and deactivation sequence through an independent sequencer * Supports the asynchronous protocols T = 0 and T = 1 in accordance with ISO 7816, Europay, Mastercard and Visa (EMV) * Supports synchronous cards * Short circuit current limiting * Special circuitry for killing spikes during power-on or off * Supply supervisor for power-on/off reset * Step-up converter (supply voltage from 4.2 to 6 V) * Power-down and sleep mode for low power consumption * Enhanced ESD protection on card side (6 kV minimum) * Software library for easy integration within the application. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA8006H/C1 TDA8006H/C2 TDA8006H/C3 TDA8006AH/C1 TDA8006AH/C2 TDA8006AH/C3 QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm QFP64 DESCRIPTION plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm APPLICATIONS TDA8006 * Smart card readers for multiprotocol applications (EMV banking, digital pay TV, access control, etc.). GENERAL DESCRIPTION It is assumed that the reader of this data sheet is familiar with ISO 7816. The TDA8006 is controlled either through a standard serial interface or a parallel bus, it takes care of all ISO 7816, EMV and GSM11.11 requirements. It gives the card and the set a very high level of security due to its special hardware against ESD, short circuit, power failure, etc. Its integrated step-up converter allows operation within a supply voltage range of 4.2 to 6 V. A special version of the TDA8006 is available which has its internal connections to the controller accessible through external pins. This allows easy development and evaluation when used with a 80CL580 microcontroller or a development tool. An emulation board is available. A software library has been developed, taking care of all actions required for T = 0, T = 1 and synchronous protocols. This library may be either linked with the application software before masking, or masked in the internal ROM (see "Application Note AN98106"). VERSION SOT319-2 SOT307-2 2000 Oct 30 2 Philips Semiconductors Product specification Multiprotocol IC Card coupler QUICK REFERENCE DATA SYMBOL VDD IDD(pd) IDD(sm) VCC PARAMETER supply voltage supply current in power-down mode VDD = 5 V; card inactive; note 1 supply current in sleep mode card supply voltage card powered but clock stopped; note 1 including static loads (5 V card) with 40 nAs dynamic loads on 100 nF capacitor (5 V card) including static loads (3 V card) with 24 nAs dynamic loads on 100 nF capacitor (3 V card) ICC SR card supply current slew rate (rise and fall) operating overload detection maximum load capacitor pin VCC 400 nF (including typical 100 nF decoupling) CONDITIONS MIN. 4.2 - - 4.75 4.6 2.80 2.75 - - 0.10 TYP. - - - 5.0 - - - - 80 0.16 TDA8006 MAX. 6 250 1500 5.25 5.4 3.20 3.25 65 - 0.30 UNIT V A A V V V V mA mA V/s tde tact fxtal foper Tamb Note deactivation cycle duration activation cycle duration crystal frequency operating frequency operating ambient temperature external frequency applied on pin XTAL1 - - 4 0 -25 - - - - - 100 225 25 25 +85 s s MHz MHz C 1. IDD in all configurations include the current at pins VDD, VDDA and VDDRAM. 2000 Oct 30 3 Philips Semiconductors Product specification Multiprotocol IC Card coupler BLOCK DIAGRAM TDA8006 handbook, full pagewidth VDD 100 nF GND S1 29 (19) 100 nF S2 31 (21) VDDA AGND 30 (20) 28 (18) TDA8006H (TDA8006AH) ALARM CDELAY 45 (32) 44 (31) 41(28) 40 (27) SUPPLY AND SUPERVISOR STEP-UP CONVERTER (22) 32 VUP 100 nF RESET PSEN ALE EA P36/WR P37/RD 52 (34) 7 (3) 8 (4) 11 (7) 61 (41) 62 (42) 19 to 12 (11 to 8)(1) 63, 64, 1 to 6 (43, 44, 1, 2)(2) MICROCONTROLLER 80C52 16-kbyte ROM 256-byte RAM 58 (38) 59 (39) 60 (40) 53 (35) 54 (36) (24) 37 INT0 6 8 P40 to P47 INTERNAL OSCILLATOR I/O (23) 36 VCC ANALOG DRIVERS AND SEQUENCER (16) 26 RST P35 C8 (26) 39 C8 P34 C4 (25) 38 C4 P00 to P07 (17) 27 CLK P20 to P27 P30/RXD P31/TXD P33/INT1 P10/T2 P11/T2EX PERIPHERALS (29) 42 PRES VDDRAM GNDRAM 23 (14) 24 (15) 1024 AUX RAM T = 0,1 ISO UART I/O OFF 3 V/5 V CMDVCC CLKOUT 43 (30) CLOCK CIRCUITRY 10 (6) XTAL1 9 (5) XTAL2 PORT EXTENSION 48 to 51(3) MGR225 K0 to K3 Minimum value for capacitor between VDDA and AGND is 2.2 F. Pin numbers in parenthesis represent the TDA8006AH. (1) Ports P04 to P07 not applicable for QFP44 package. (2) Ports P24 to P27 not applicable for QFP44 package. (3) Ports K0 to K3 not applicable for QFP44 package. Fig.1 Block diagram. 2000 Oct 30 4 Philips Semiconductors Product specification Multiprotocol IC Card coupler PINNING PIN SYMBOL QFP64 P22 P23 P24 P25 P26 P27 PSEN ALE XTAL2 XTAL1 EA P07 P06 P05 P04 P03 P02 P01 P00 n.c. n.c. n.c. VDDRAM GNDRAM n.c. RST CLK AGND S1 VDDA S2 VUP n.c. n.c. n.c. VCC 2000 Oct 30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 QFP44 1 2 - - - - 3 4 5 6 7 - - - - 8 9 10 11 12 13 - 14 15 - 16 17 18 19 20 21 22 - - - 23 address 10/general purpose I/O port address 11/general purpose I/O port address 12/general purpose I/O port address 13/general purpose I/O port address 14/general purpose I/O port address 15/general purpose I/O port program store enable output address latch enable crystal connection crystal connection or external clock input external access address/data 7/general purpose I/O port address/data 6/general purpose I/O port address/data 5/general purpose I/O port address/data 4/general purpose I/O port address/data 3/general purpose I/O port address/data 2/general purpose I/O port address/data 1/general purpose I/O port address/data 0/general purpose I/O port not connected not connected not connected supply voltage for the auxiliary RAM ground for the auxiliary RAM not connected card reset output (ISO contact C2) clock output to the card (ISO contact C3) ground for the analog part DESCRIPTION TDA8006 contact 1 for the step-up converter (a ceramic capacitor of 100 nF must be connected between S1 and S2) analog supply voltage for the voltage doubler contact 2 for the step-up converter (a ceramic capacitor of 100 nF must be connected between S1 and S2) output of the step-up converter; must be decoupled with a 100 nF ceramic capacitor not connected not connected not connected card supply output voltage (ISO contact C1) 5 Philips Semiconductors Product specification Multiprotocol IC Card coupler TDA8006 PIN SYMBOL QFP64 I/O C4 C8 GND VDD PRES CLKOUT CDELAY ALARM TEST INHIB K0 K1 K2 K3 RESET P10/T2 P11/T2EX n.c. n.c. n.c. P30/RXD P31/TXD P33/INT1 P36/WR P37/RD P20 P21 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 QFP44 24 25 26 27 28 29 30 31 32 33 - - - - - 34 35 36 37 - - 38 39 40 41 42 43 44 data line to/from the card (ISO contact C7) auxiliary I/O for ISO contact C4 (synchronous cards for example) auxiliary I/O for ISO contact C8 (synchronous cards for example) ground supply voltage card presence contact input (active HIGH or LOW by mask option); see Table 12 output for clocking external devices external capacitor connection for delayed reset signal open drain reset output (active HIGH or LOW by mask option); see Table 12 test pin (must be left open-circuit in the application) test pin (must be left open-circuit in the application) output port from port extension (2 mA push-pull) output port from port extension (2 mA push-pull) output port from port extension (2 mA push-pull) output port from port extension (2 mA push-pull) input for resetting the microcontroller (active HIGH) general purpose I/O port (connected to P10) general purpose I/O port (connected to P11) not connected not connected not connected general purpose I/O port or serial interface receive line general purpose I/O port or serial interface transmit line general purpose I/O port or interrupt (connected to P33) general purpose I/O port or external data memory write strobe general purpose I/O port or external data memory read strobe address 8/general purpose I/O port address 9/general purpose I/O port DESCRIPTION 2000 Oct 30 6 Philips Semiconductors Product specification Multiprotocol IC Card coupler TDA8006 60 P33/INT1 58 P30/RXD 59 P31/TXD 61 P36/WR handbook, full pagewidth 54 P11/T2EX 62 P37/RD 52 RESET 51 K3 50 K2 49 K1 48 K0 47 INHIB 46 TEST 45 ALARM 44 CDELAY 43 CLKOUT 42 PRES 41 VDD 40 GND 39 C8 38 C4 37 I/O 36 VCC 35 n.c. 34 n.c. 33 n.c. VUP 32 P22 P23 P24 P25 P26 P27 PSEN ALE XTAL2 1 2 3 4 5 6 7 8 9 XTAL1 10 EA 11 P07 12 P06 13 P05 14 P04 15 P03 16 P02 17 P01 18 P00 19 n.c. 20 n.c. 21 n.c. 22 VDDRAM 23 GNDRAM 24 TDA8006H n.c. 25 RST 26 CLK 27 AGND 28 S1 29 VDDA 30 S2 31 53 P10/T2 64 P21 63 P20 57 n.c. 56 n.c. 55 n.c. MGR226 Fig.2 Pin configuration (QFP64). 2000 Oct 30 7 Philips Semiconductors Product specification Multiprotocol IC Card coupler TDA8006 40 P33/INT1 38 P30/RXD 39 P31/TXD 41 P36/WR 42 P37/RD handbook, full pagewidth 36 P11/T2EX 34 RESET 35 P10/T2 44 P21 43 P20 37 n.c. P22 1 P23 2 PSEN 3 ALE 4 XTAL2 5 XTAL1 6 EA 7 P03 8 P02 9 P01 10 P00 11 33 TEST 32 ALARM 31 CDELAY 30 CLKOUT 29 PRES TDA8006AH 28 VDD 27 GND 26 C8 25 C4 24 I/O 23 VCC S2 21 VDDRAM 14 GNDRAM 15 AGND 18 VDDA 20 VUP 22 n.c. 12 n.c. 13 RST 16 CLK 17 S1 19 MGR227 Fig.3 Pin configuration (QFP44). 2000 Oct 30 8 Philips Semiconductors Product specification Multiprotocol IC Card coupler FUNCTIONAL DESCRIPTION Microcontroller The microcontroller is an 80C52 with 16 kbytes of ROM, 256 byte RAM, timers 0, 1, 2 , and 5 I/O ports (port P0: open-drain; ports P1 to P3: weak pull-up). Port P4 is identical to 83CE560, except that precharge circuits ensure fast rise times at end of read mode (transition times <0.5 s). The ROM code content can be tested by signature to avoid reading it out after masking; for security bit option, see Table 12. The CPU, timers 0 and 1, serial UART, parallel I/O ports, 256 byte RAM, 16 kbyte ROM and external bus are conventional C51 family library elements. Timer 2 is a conventional C52 element (interrupt enable bit ET2: bit 3 in register IEN1 at byte address E8H and interrupt priority bit PT2: bit 3 in register IP1 at byte address F8H. TDA8006 Register PCON has an added feature: PCON.5 = RFI (reduced Radio Frequency Interference bit). When set to logic 1, pin ALE cannot be toggled. ALE clears on RESET. If access is required to the external data memory via MOVX instructions (see Table 1), set bit PCON.6 = ARD in the PCON register to logic 1. For further information, please refer to the published specification of the 83CE560 in "Data Handbook IC20; 80C51-Based 8-Bit Microcontrollers". Ports P40 to P47, INT0 and P12 to P17 are used internally for controlling the smart card interface and the other peripherals. Ports P34 and P35 are used to control the auxiliary contacts C4 and C8. The list of differences given in Table 1 may help the software developer of the dedicated emulation board for the TDA8006 or other devices. Table 1 List of differences between TDA8006, CE560, CL580 and C52 FEATURES TDA8006 C0 Intel 16 kbytes 0003H 000BH 2nd 0013H 001BH 4th 0023H 5th 004BH lowest (6th) no no no no no no 1 kbyte peripheral reset, INT0, INT1 C0 Philips 64 kbytes 0003H highest (1st) 000BH 2nd 0013H 3th 001BH 4th 0023H 5th 0033H, etc. (8) miscellaneous yes yes yes yes yes no 2 kbyte MOVX reset, INT0, INT1 + other 83CE560 C1 Intel 6 kbytes 0003H highest (1st) 000BH 4th 0013H 7th 001BH 10th 0023H 13th 0033H 5th yes yes no yes yes yes no reset, INT2 to INT8 CL580 no Intel 8 kbytes 0003H highest (1st) 000BH 2nd 0013H 3th 001BH 4th 0023H 5th 002BH lowest (6th) no no no no no no no reset INTEL C52 P4 address Timer 2 ROM size External 0 interrupt vector Timer 0 interrupt vector Timer 0 interrupt priority External 1 interrupt vector Timer 1 interrupt vector Timer 1 interrupt priority Serial 0 interrupt vector Serial 0 interrupt priority Timer 2 interrupt vector Timer 2 interrupt priority I2C-bus ADC 32 kHz oscillator PWM Watchdog Interrupts on P1 Additional RAM Wake-up from power-down mode External 0 interrupt priority highest (1st) External 1 interrupt priority 3th 2000 Oct 30 9 Philips Semiconductors Product specification Multiprotocol IC Card coupler Table 2 Special function register bit addresses X = don't care. BYTE REGISTER ADDRESS (HEX) IP1 B IEN1 ACC PSW T2CON P4 IP0 P3 IEN0 P2 SCON P1 TCON P0 F8 F0 E8 E0 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 BIT ADDRESS [HEX] BIT FUNCTION MSB [FF] - [F7] - [EF] - [E7] - [D7] CY [CF] TF2 [C7] - [BF] - [B7] - [AF] EA [A7] - [9F] SM0 [97] - [8F] TF1 [87] - [FE] - [F6] - [EE] - [E6] - [D6] AC [CE] EXF2 [C6] - [BE] - [B6] - [AE] - [A6] - [9E] SM1 [96] - [8E] TR1 [86] - [FD] - [F5] - [ED] - [E5] - [D5] F0 [CD] RCLK [C5] - [BD] - [B5] - [AD] - [A5] - [9D] SM2 [95] - [8D] TF0 [85] - [FC] - [F4] - [EC] - [E4] - [D4] RS1 [CC] TCLK [C4] - [BC] PS0 [B4] - [AC] ES0 [A4] - [9C] REN [94] - [8C] TR0 [84] - [FB] PT2 [F3] - [EB] ET2 [E3] - [D3] RS0 [CB] [C3] - [BB] PT1 [B3] - [AB] ET1 [A3] - [9B] TB8 [93] - [8B] IE1 [83] - [FA] - [F2] - [EA] - [E2] - [D2] OV [CA] [C2] - [BA] PX1 [B2] - [AA] EX1 [A2] - [9A] RB8 [92] - [8A] IT1 [82] - [F9] - [F1] - [E9] - [E1] - [D1] F1 [C9] C/T2N [C1] - [B9] PT0 [B1] - [A9] ET0 [A1] - [99] TI [91] - [89] IE0 [81] - - [F0] - [E8] - [E0] - [D0] P [C8] LSB [F8] TDA8006 BIT RESET VALUE XXXX 0XXX 0000 0000 0000 0000 0000 0000 0000 0000 EXEN2 TR2 CP/RL2N 0000 0000 [C0] - [B8] PX0 [B0] - [A8] EX0 [A0] - [98] RI [90] - [88] IT0 [80] - 1111 1111 0000 0000 1111 1111 0000 0000 1111 1111 0XX0 0000 1111 1111 XXX0 0000 1111 1111 2000 Oct 30 10 Philips Semiconductors Product specification Multiprotocol IC Card coupler Table 3 Other register byte addresses BYTE ADDRESS (HEX) 81 82 83 87 89 8A 8B 8C 8D 99 CA CB CC CD BIT RESET VALUE 0000 0111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 XXXX XXXX 0000 0000 0000 0000 0000 0000 0000 0000 Step-up converter TDA8006 An integrated spike killer ensures the contacts to the card remain inactive during power-up or power-down. An internally generated voltage reference is used by the step-up converter, the voltage supervisor and the VCC generator. If VDD is too low to ensure proper operation, the voltage supervisor generates an alarm pulse, whose length is defined by an external capacitor tied to the CDELAY pin, (1 ms per 1 nF typical). This pulse is used to reset the controller and is used in parallel with an external reset input which can come from the system controller. It is also used to either block any spurious on-card contacts during a controller reset or to force an automatic deactivation of the contacts in the event of supply drop-out (see Sections "Activation sequence" and "Deactivation sequence"). It is also fed to an external open-drain output (called ALARM) which can be chosen active HIGH or LOW by mask option (see Table 12). REGISTER SP DPL DPH PCON TMOD TL0 TL1 TH0 TH1 S0BUF RCAP2L RCAP2H TL2 TH2 Supply The circuit operates within a supply voltage range of 4.2 to 6 V. The supply pins are VDD, VDDA, GND, AGND, VDDRAM and GNDRAM. Pins VDDA and AGND supply the card analog drivers and have to be externally decoupled because of the large current spikes that the card and the step-up converter can create. VDDRAM and GNDRAM supply the auxiliary RAM and should be decoupled separately. VDD and GND supply the rest of the chip. Except for the VCC generator and the other card contact buffers, the whole circuit is powered by VDD, VDDA and VDDRAM. If the supply voltage is 4.2 V, then a higher voltage is needed for the supply to the ISO contacts. When a card session is requested by the controller, the sequencer first starts the step-up converter. This uses switched capacitors which are clocked at a frequency of approximately 2.5 MHz by an internal oscillator. The output voltage VUP is regulated at approximately 6 V and then fed to the VCC generator. VCC and GND are used as a reference for all other card contacts. handbook, full pagewidth VDD Vth(VDD) CDELAY Vth(CDELAY) ALARM tW MGR228 Fig.4 Voltage supervisor. 2000 Oct 30 11 Philips Semiconductors Product specification Multiprotocol IC Card coupler ISO 7816 security The correct sequence during activation and deactivation of the card is ensured by a specific sequencer clocked at a frequency which is a division ratio of the internal oscillator. Activation (bit CMDVCC within the ports extension register HIGH) is only possible if the card is present (pin PRES HIGH or LOW according to the mask option) and if the supply voltage is correct (ALARM signal inactive). The presence of the card is signalled to the controller by the OFF bit (within the UART status register), generating an interrupt, if enabled, when toggling. During a session, the sequencer performs an automatic emergency deactivation in the event of card take-off, supply voltage drop or short circuit. The OFF bit goes LOW, thereby warning the controller through the interrupt line INT0 and the status register. Peripheral interface (see Figs 5 and 6) This block allows parallel communication with the four peripherals (ISO 7816 UART, clock generator, on/off sequencer and auxiliary RAM) through an 8-bit data bus, 6-bit address and control bus and one interrupt line to the controller. The data bus consists of ports P40 (data bit 0) to P47 (data bit 7). The address bus consists of ports AD0 (P12), AD1 (P13), AD2 (P14) and AD3 (P15). The control lines are R/W (P16) and EN (P17). The interrupt line is INT0. During a read operation, EN goes LOW allowing the controller to read data on the bus. During a write operation, the data should be present on the bus before asserting EN LOW which allows the data to be written to the registers. TDA8006 After resetting EN HIGH, the controller must release the bus by setting port P4 HIGH again (the transition times on port P4 are less than 500 ns). The interrupt line is reset HIGH when reading out the status register. READ OPERATION * Set port P4 to FFH * Select the register with AD0, AD1, AD2, AD3 * Assert R/W HIGH * Assert EN LOW; the data is available on data bus P4 * Read the data on port P4 * Set EN HIGH; the bus is set to high impedance. WRITE OPERATION * Select the correct register with AD0, AD1, AD2, AD3 * Assert R/W LOW * Write data to the data bus port P4 * Assert EN LOW; the data is written to the register * Set EN HIGH * Set port P4 to FFH; the bus is set to high impedance. Integrated precharges allow fast rising edges on port P4 when changing from read mode to write mode, thus avoiding the need to trigger the active pull-ups on port P4. handbook, full pagewidth P4 XX FF DATA FF DATA FF R/W AD0 to AD3 X AD AD EN read data cycle write data cycle MGR229 Fig.5 Use of peripheral interface. 2000 Oct 30 12 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2000 Oct 30 8 8 P00/P07 P32/INT0 P17 P34 P35 P16 P40 to P47 P20/P27 PSEN ALE EA P37/RD P36/WR 80C52 CORE P15 P14 P13 P12 AD3 AD2 AD1 AD0 EN EN INT AD3 AD2 AD1 AD0 R/W R/W Philips Semiconductors AD3 AD2 AD1 AD0 EN AD0 AD1 AD2 AD3 R/W TRANSMIT REGISTER RECEIVE REGISTER STATUS REGISTER SYNCHRONOUS IN REGISTER SYNCHRONOUS OUT REGISTER GUARD TIME REGISTER CONFIGURATION REGISTER ISO 7816 UART PERIPHERAL EXTENSION REGISTER ON/OFF SEQUENCER CLOCK CONFIGURATION REGISTER PROGRAMMABLE DIVIDER CLOCK GENERATOR MICRO CLOCK UART CARD EXTERNAL CLOCK CLOCK CLOCK XTAL LOW ADDRESS REGISTER HIGH ADDRESS REGISTER MEMORY READ REGISTER MEMORY WRITE REGISTER AUXILIARY RAM MGR230 I/O C4 C8 K0 K1 K2 K3 CMDVCC RST DET ERR POR INTERFACE, SECURITY AND POWER CONTROL CLK CLKOUT OSCINT XTAL1 R/W EN handbook, full pagewidth Multiprotocol IC Card coupler P30/RXD P31/TXD P10/T2 P11/T2EX P33/INT1 RESET OSC 8 databus control bus 13 Product specification TDA8006 Fig.6 Peripheral interface. Philips Semiconductors Product specification Multiprotocol IC Card coupler Table 4 Register addresses X = don't care. AD3 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Clock circuit The microcontroller clock (OSC), the card clock (CLK), the ISO 7816 UART clock, and the clock to the external world (CLKOUT), are derived from the main clock signals (XTAL from 4 to 20 MHz, or an external clock signal applied to XTAL1), or the internal oscillator (fINT). * Microcontroller clock (OSC): after power-on or reset, the microcontroller is clocked at 18fINT. Then, the application may decide to clock it at 12fINT, 12fxtal or fxtal. All frequency changes are synchronous, thereby ensuring no hang-up due to short spikes etc. * Card clock (CLK): the application may send a clock frequency of 12fxtal, 14fxtal, 18fxtal or 12fINT (1.25 MHz), or may stop the clock at HIGH or LOW. All transitions are synchronous, ensuring correct pulse length during start or change, in accordance with ISO 7816. After power-on or reset, CLK is held LOW. * External clock output (CLKOUT): CLKOUT is a permanent clock output for external use. The following frequencies are possible: fxtal, 12fxtal and 14fxtal. All transitions are synchronous. After power-on or reset, CLKOUT is fixed at 14fxtal. * ISO 7816 UART clock: the clock to the ISO 7816 UART is identical to the clock to the card (CLK). AD2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 AD1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 AD0 0 1 1 1 0 0 1 1 0 1 X X X X R/W 0 0 0 1 0 1 1 0 0 0 0 0 0 1 REGISTER CCR (Clock Configuration Register) PDR (Programmable Divider Register) SOR (Synchronous Output Register) SIR (Synchronous Input Register) UTR (UART Transmit Register) URR (UART Receive Register) USR (UART Status Register) UCR (UART Configuration Register) GTR (Guard Time Register) PER (Ports Extension Register) MAR0 (Memory Address LOW) MAR1 (Memory Address HIGH) MWR (Memory Write Register) MRR (Memory Read Register) TDA8006 PERIPHERAL clock generator ISO 7816 UART on/off sequencer auxiliary RAM To achieve the different I/O baud rates as defined by values F and D (see Table 7), the clock signal is counted by an auto-reload 8-bit programmable counter and then divided by a 31 or 32 prescaler. All these configurations are controlled by the clock configuration register and by the programmable divider register. 2000 Oct 30 14 Philips Semiconductors Product specification Multiprotocol IC Card coupler Table 5 Clock Configuration Register (CCR; address 0; write only; all bits cleared after reset) X = don't care. D7 X X X X X X X X X X X 0 0 1 1 D6 X X X X X X X X X X X 0 1 0 1 D5 X X X X X X X X 0 0 1 X X X X D4 X X X X X X X X 0 1 0 X X X X D3 X X 0 0 0 0 1 1 X X X X X X X D2 X X 0 0 1 1 0 0 X X X X X X X D1 X X 0 1 0 1 0 1 X X X X X X X D0 0 1 X X X X X X X X X X X X X UART PRESCALER /31 /32 STOP LOW 1 1 1 1 2fxtal 4fxtal 8fxtal 2fINT 1 TDA8006 CLK CLKOUT OSC STOP HIGH 4fxtal fxtal 1 f 2 xtal 1 8fINT fxtal 1 f 2 xtal 1 f 2 INT The hexadecimal value stored in the Programmable Divider Register (PDR) is the auto-reload value of an 8-bit counter clocked by the card clock (CLK); when the value is loaded in the counter, it counts from this value till overflow; then it is reloaded with the same value and the count restarts. The output of the counter is then divided by 31 or 32 depending on the programmed value of the UART prescaler. The result is the ISO 7816 UART CLK which is used for shifting the data in or out on the I/O line. The example shown in Fig.7 shows how to program a division factor of 372. With these registers, the baud rates given in Table 7 are achieved according to ISO 7816. The division ratio of 31 or 32 depends on which prescaler is selected, and the hexadecimal value is the value programmed within the PDR. Table 6 D7 n7 Note 1. A division factor of F4H, for example, would be 1111 0100 reading from D7 to D0. Programmable Divider Register (PDR; address 1; write only; all bits cleared after reset) D6 n6 D5 n5 D4 n4 D3 n3 D2 n2 D1 n1 D0 n0 DIVISION FACTOR n7n6n5n4 n3n2n1n0(1) 2000 Oct 30 15 Philips Semiconductors Product specification Multiprotocol IC Card coupler TDA8006 handbook, full pagewidth /31 CLK 8-BIT AUTO-RELOAD COUNTER WITH PDR = F4H ISO 7816 UART CLK /32 MGR231 Fig.7 Baud rate selection on I/O. Table 7 Selecting baud rate using F and D values Baud rate is selected by values D and F shown in parenthesis. The PDR is loaded with a value shown in Hexadecimal, and either prescaler 31 or 32 is selected. PDR VALUE [VALUE D] PRESCALER /31 [VALUE F] PRESCALER /32 [VALUE F] [0000] [0001] [0010] [0011] [0100] [0101] [0110] [1001] [1010] [1011] [1100] [1101] [0001] [0010] [0011] [0100] [0101] [0110] [1000] [1001] F4 FA FD - - - FF - F4 FA FD - - - FF - EE F7 - - - - - - E8 F4 FA FD - - FE - DC EE F7 - - - FD - D0 E8 F4 FA FD - FC - C4 E2 F1 - - - FB FD F0 F8 FC FE FF - - - E8 F4 FA FD - - FE - E0 F0 F8 FC FE FF - - D0 E8 F4 FA FD - FC - C0 E0 F0 F8 FC FE - - 2000 Oct 30 16 Philips Semiconductors Product specification Multiprotocol IC Card coupler On/off controller Table 8 BIT D0 D1 D2 On/off controller bits (PER; address 7; write only; all bits cleared after reset) NAME CMDVCC; set and reset by software RSTIN; set and reset by software Force Inverse Parity (FIP); set and reset by software DESCRIPTION TDA8006 set to 1 for starting activation sequence of the card, and reset to 0 for starting deactivation control line RST for card contact C2 in manual mode (active HIGH) when LOW, the UART processes the parity according to ISO 7816; when HIGH, the UART processes the inverse parity (which causes parity errors during transmission and `not acknowledge' signals during reception) when HIGH, the UART automatically counts the clock pulses during ATR and controls the RST contact; this bit is automatically reset by hardware when a start bit is detected on I/O or when the card is declared as mute; when LOW, this automatic processing is disabled (manual mode) auxiliary 2 mA push-pull output control (inverted output) auxiliary 2 mA push-pull output control (inverted output) auxiliary 2 mA push-pull output control (inverted output) auxiliary 2 mA push-pull output control (inverted output) ISO 7816 UART The ISO 7816 UART handles all specific requirements defined in ISO 7816 T = 0 and T = 1 protocol types. It is also able to deal with synchronous cards (in conjunction with contacts C4 and C8). In addition, there is a possibility to force parity errors for test purposes or flow control. The counting of CLK cycles during ATR is possible by either hardware or software. The ISO 7816 UART is configured with 2 registers: UART Configuration Register (UCR) and Guard Time Register (GTR). When timings are given in terms of ETU (Elementary Time Unit as defined by ISO 7816), then the reference is the negative edge of the start bit of the character being received or transmitted, unless otherwise specified. D3 automatic ATR processing enabling (ATREN); set by software, reset by hardware D4 D5 D6 D7 K0; set and reset by software K1; set and reset by software K2; set and reset by software K3; set and reset by software The on/off controller is used for activating or deactivating the card, for controlling contact C2 (RST) manually through RSTIN or automatically, for forcing inverse parity (for flow control or test purposes), and for controlling four independent push-pull output lines K0 to K3. After having cleared the ISO 7816 UART reset bit (see UART configuration register) and checking the card presence within the status register, the software may initiate an activation sequence by setting bit CMDVCC HIGH. It may also initiate a deactivation sequence by resetting this bit (see activation and deactivation sequences). The timings during the ATR may be checked either manually (using RSTIN and t3/t5 for counting clock pulses) or automatically by setting bit ATREN HIGH (see Section "Activation sequence"). In this case, hardware controls both RST and the counting of CLK pulses. Bit ATREN is reset by hardware when a start bit has been detected before 2 x 40100 CLK pulses for versions C2 and C3 (2 x 45000 CLK pulses for version C1), or when the card is declared as `mute'. Setting this bit HIGH again during a session initiates a warm reset. A warm reset may also be done manually by using RSTIN and t3/t5 again. 2000 Oct 30 17 Philips Semiconductors Product specification Multiprotocol IC Card coupler Table 9 BIT D0 D1 UART Configuration Register (UCR; address 5; write only; all bits cleared after reset) NAME Reset ISO 7816 UART (RIUN); set by software, reset by software Start Session (SS); set by software, reset by software DESCRIPTION TDA8006 when LOW, this bit resets the UART; must be set by software before any use of the UART when HIGH, this bit allows the detection of the convention during the initial character of the card; must be reset by software after correct reception of the first character and before complete reception of the next character when HIGH, this bit allows automatic toggling from transmission to reception mode after successful transmission of the last character; in this case, TRN is also reset by hardware when LOW, the UART is in reception mode; when HIGH, it is in transmission mode; INT goes LOW when TRN is set when LOW, the UART is in T = 0 mode; when HIGH, the UART is in T = 1 mode when LOW, the card supply voltage VCC = 5 V; when HIGH, VCC = 3 V when HIGH, this bit allows direct monitoring of I/O by bit D0 of SIR or SOR; when LOW, I/O is fed to the ISO 7816 UART For the next characters, bit RBF is set at 10.5 ETU and an interrupt is generated, if enabled, to indicate that a character has been received, with or without parity error, and that this character may be read within the reception register. The interrupt is cleared on the falling edge of EN during the read operation of the received character. In protocol type T = 0 (bit PS LOW), the I/O line is automatically pulled LOW between 10.5 and 11.75 ETU if a character parity error is detected (parity error handling at character level). In protocol type T = 1 (bit PS HIGH), if a parity error is detected, bit PE is set in the status register, but the I/O line is not pulled LOW. D2 Last Character to Transmit (LCT); set by software, reset by hardware or software Transmit/Receive-N (TRN); set by software, reset by software or hardware not used Protocol Selection (PS); set by software, reset by software 3 V/5 V-N (TFN); set by software, reset by software Synchrone/asynchrone-N (SAN); set by software, reset by software D3 D4 D5 D6 D7 RECEPTION In order to start a session with the card, bit RIUN (which resets the ISO 7816 UART when LOW) must be set HIGH. The UART recognizes the convention (direct or inverse) of the characters received while bit SS (Start Session) is HIGH. Then the UART automatically converts any transmitted or received character according to this convention, so the software only has to deal with characters written in direct convention. Indeed, bit SS must be reset by software after correct receipt of the first character of the ATR (TS) and before complete receipt of the next character. Reception mode is selected when TRN is LOW. Bit FSD is set within the UART Status Register (USR), and an interrupt is generated, if enabled, at the start bit of the received character when SS is HIGH, allowing the manual CLK count during ATR. The interrupt will be cleared on the rising edge of EN during the status read operation. 2000 Oct 30 18 Philips Semiconductors Product specification Multiprotocol IC Card coupler TDA8006 handbook, full pagewidth RIU SS CMDVCC R/W P4 FF FF FF FF FF EN I/O INT FSD RBF 10.5 ETU release reset set CMDVCC first start read status set start session int cleared anything buffer full read status read character and int cleared reset start session MGR232 Fig.8 First character reception. TRANSMISSION Transmission mode is selected when TRN is HIGH. If enabled, an interrupt occurs on the rising edge of TRN, indicating that the transmission buffer is empty and ready to accept a character for transmission. The interrupt is cleared during the read status operation. The character is written to the UTR on the falling edge of EN during the write operation, and starts to be transmitted on the rising edge of EN. The I/O line is read at 10.84 ETU to check if the card has detected a parity error. At the same time, bit TBE is set in the USR, and, if enabled, an interrupt occurs to indicate that the transmission buffer is empty, and that a new character may be written. If the parity is correct, the transmission of the next character will start at 12 ETU + GT + 0.5 ETU after the start bit of the previous 2000 Oct 30 19 character (see Section "Extra guard time"). If the parity is not correct, then assuming that a character has been written to the UTR, the transmission starts at 13 ETU (the guard time GT must be programmed before transmitting). Bit LCT can be used for cards that are required to change from transmission to reception mode very fast. If LCT is set HIGH, then the UART automatically resets bits TRN and LCT at 10.85 ETU if no parity error has occurred; the UART is ready to receive a character from the card at 12 ETU (T = 0) or 11 ETU (T = 1) after the previous start bit. If a parity error has occurred during transmission of the last character, then the UART stays in transmission mode with LCT set, waiting for the software to rewrite the corrupted character. Philips Semiconductors Product specification Multiprotocol IC Card coupler TDA8006 handbook, full pagewidth R/W P4 FF FF FF FF FF EN TRN LCT TBE INT I/O anything read status int cleared transmission write character start transmit buffer empty read status int cleared write character set LCT anything start transmit buffer empty start receive TRN/LCT reset MGR233 Fig.9 Character transmission with or without LCT. SYNCHRONOUS CARDS If bit SAN (Synchronous/Asynchronous-N) is set, the software can operate with synchronous cards; the information available on the I/O line is copied on data bit 0 of the data bus without entering the UART when either registers SIR or SOR are selected. At the end of a transmission in synchronous mode, it is necessary to switch back to synchronous reception mode by reading register SIR. The synchronous clock may be controlled by selecting CLK STOP HIGH or STOP LOW. Contacts C4 and C8 may be controlled by ports P34 and P35 (operation depends on synchronous card type). Synchronous Input Register (SIR; address 3; read only) When this register is selected, I/O is copied on data bit 0 (P40) and may be read by the controller. Synchronous Output Register (SOR; address 3; write only) When this register is selected, I/O is copied on data bit 0 (P40) on the falling edge of EN. 2000 Oct 30 20 Philips Semiconductors Product specification Multiprotocol IC Card coupler TDA8006 handbook, full pagewidth R/W P4 FF FF P40 CLK EN I/O read write MGR234 Fig.10 Using synchronous cards. EXTRA GUARD TIME Between the transmission of two characters to the card, the ISO 7816 UART automatically inserts a number of guard ETUs equal to the value, called GT, stored in the GTR, see Table 10. For a GT of FAH, for example, the value would be 1111 1010 reading from D7 to D0. A GT of FFH has a special status which means 0 ETU when the protocol is T = 0 and -1 ETU when the protocol is T = 1 (reception and transmission is possible at 11 ETU). Table 10 Guard Time Register (GTR; address 6; write only; all bits cleared after reset) D7 n7 D6 n6 D5 n5 D4 n4 D3 n3 D2 n2 D1 n1 D0 n0 GUARD TIME VALUE (GT) n7n6n5n4 n3n2n1n0 start bit. This overwrites the previous character which should have been read by the controller. * The UART checks the parity of the received characters; if the parity is wrong, then bit PE is set in the status register at the same time as bit RBF (Receive Buffer Full). * In protocol T = 0, I/O is pulled LOW between 10.5 and 11.75 ETU in case of error. Characters may be received from the card every 12 ETU, even after a transmission (see LCT; Table 9). In protocol T = 1, reception is possible at 11 ETU. 21 UART receive and transmit registers UART Receive Register (URR; address 4; read only; all bits cleared after reset) D7 to D0 are the data bits received from the card. Because the UART automatically converts the characters according to the convention recognized during TS, all characters in the URR are in direct convention. * The received character is loaded in the URR 0.5 ETU after the parity shift, i.e. 10.5 ETU after the edge of the 2000 Oct 30 Philips Semiconductors Product specification Multiprotocol IC Card coupler UART Transmit Register (UTR; address 4; write only; all bits cleared after reset) Bits D7 to D0 are the data bits to be transmitted to the card. Due to the automatic conversion performed by the UART according to the convention detected during TS, the controller must write the characters to send to the card in direct convention. The character to be sent may be written to the UTR as soon as bit TBE (Transmit Buffer Empty) is set in the status register. If writing to the UCR occurs after 12.5 ETU + GT after the previous start bit, then the transmission starts on the rising edge of EN during the write operation. If writing to the UCR occurs before 12.5 ETU + GT after the previous start bit, the UART waits until 12.5 ETU + GT after the previous start bit before starting the transmission. In protocol T = 0, if a parity error is signalled by the card, the previous character must be rewritten to the UTR. The UART will then wait 13 ETU after the start bit of the previous character before restarting the transmission. Table 11 UART Status Register (USR; address 5; read only; all bits cleared after reset except for D5) BIT D0 NAME TX Buffer Empty (TBE) DESCRIPTION STATUS REGISTER AND INTERRUPTS TDA8006 The ISO 7816 UART reports its activity to the microcontroller through the UART status register, which acts upon the interrupt line INT. All bits except for D5 generate an interrupt on INT, if enabled, when they are set. D0, D2, D3, D4, D6 and D7 are cleared on the rising edge of EN after a read operation of the USR. D1 is cleared when the data in the reception buffer has been read-out. D5 may be used to check the card's presence and also to determine the reason for an emergency deactivation during a card's session. In case of Early Answer (EA) or Mute Card (MC) during automatic ATR processing, the card is not automatically deactivated. If enabled, an interrupt is generated, and the controller then decides to deactivate or not. this bit is set when the UART has finished transmitting the data written in the UTR (at 10.8 ETU) or on the rising edge of TRN; it is reset on the rising edge of EN during a read status operation this bit is set when the UART has finished receiving a character from the card (at 10.5 ETU); it is reset on the falling edge of EN during the read status operation this bit is set on the falling edge of the first start bit if SS = 1; it is reset on the rising edge of EN during a read status operation this bit is set when a parity error has been detected by the UART in transmission or in reception mode at the same time as TBE and RBF; it is reset on the rising edge of EN during a read status operation this bit is set if a start bit has been detected on I/O between the 200 and 400 first CLK pulses when the UART is configured in automatic ATR processing; it is reset on the rising edge of EN during a read status operation this bit is set if the card is present and reset if the card is not present; if CMDVCC is set HIGH, it may also be reset if a hardware problem causing an emergency deactivation sequence has occurred this bit is set when OFF state has changed; it is reset on the rising edge of EN during a read status operation this bit is set if a card has not answered after 80200 CLK pulses for versions C2 and C3 (90000 for version C1), when the ISO 7816 UART is configured in automatic ATR processing; it is reset on the rising edge of EN during a read status operation D1 RX Buffer Full (RBF) D2 D3 First Start Detect (FSD) Parity Error (PE) D4 Early Answer (EA) D5 OFF D6 D7 Off Interrupt (OFFI) Mute Card (MC) 2000 Oct 30 22 Philips Semiconductors Product specification Multiprotocol IC Card coupler Auxiliary RAM (MAR0, address C or D, write only; MAR1, address E or F, write only; MRR, MWR, address 8 or 9, read/write; all bits cleared after reset) In order to store data, 1 kbyte of auxiliary RAM may be accessed through the peripheral interface. The content of the RAM is undefined after reset. Note that only AD3, AD2 and AD1 must be programmed for addressing the RAM register, allowing faster operations if needed. There are two methods to address this memory: * Random method: the low order address is written in MAR0, and the high order address is written in MAR1. A write operation to MWR will write the data at the preselected address on the falling edge of EN, and a read operation to MRR will load to port P4 the data that is stored at the preselected address on the falling edge of EN. * Sequential method: once low order and high order addresses are written in MAR0 and MAR1, every read or write operation to MRR or MWR will increment the address that is stored in MAR0 and MAR1. Thus it is possible to read or write data strings within the auxiliary RAM without rewriting the addresses between 2 data bytes. The auto-increment feature is operational on the whole length of the RAM. In case of overflow, the count starts again at address 00H. Output Ports Extension Register (PER, address 7, write only; all bits cleared after reset) In this register, the four low order bits control the activation of the card. The four high order bits D4, D5, D6 and D7 each control auxiliary 2 mA push-pull output ports, which can be used for any purpose (LEDs, control signals, etc.). The electrical state of a port is HIGH if the bit is LOW, and LOW if the bit is HIGH. The bits are cleared after reset making the ports HIGH. Activation sequence TDA8006 When the card is inactive, pins VCC, CLK, RST and I/O are LOW, having low impedance with respect to GND. The step-up converter is stopped. The I/O is configured in reception mode with a high impedance path to the ISO 7816 UART. Any spurious pulses from the card during power-up will have no effect until I/O is enabled. When requirements are fulfilled (correct voltage supply, card present, no hardware problems), the microcontroller may initiate an activation sequence by setting bit CMDVCC HIGH (t0). * The step-up converter starts (t1) * VCC starts rising from 0 to 5 V or to 3 V with a controlled rise time of typically 0.16 V/s (t2) * I/O, contacts C4 and C8 buffers are enabled (t3); integrated pull-up resistors of 10 k are connected to VCC * CLK is sent to the card (t4) * RST buffer is enabled (t5). In order to allow a precise count of clock pulses during ATR in manual mode, a defined time window (t3/t5) is opened where the clock may be sent to the card using RSTIN. Beyond this window, RSTIN does not respond to a clock pulse, and only monitors the card's RST contact. In automatic mode (ATREN set HIGH), RST is monitored by the TDA8006, RSTIN is inactive and CLK is output by the TDA8006 at t3. RST is LOW. If the card has not responded within the period of 40100 CLK pulses for versions C2 and C3 (45000 for version C1), RST is set HIGH for a maximum of 40100 CLK pulses for versions C2 and C3 (45000 for version C1). It is also possible to customize the activation sequence by keeping CLK STOP LOW with RSTIN LOW beyond t5, and then output CLK using the CLK configuration. The sequencer is clocked by 164fINT which gives a time interval T of typically 25 s. Thus t1 = 0 to 164T, t2 = t1 + T, t3 = t1 + 4T, t4 = t3 to t5 and t5 = t1 + 7T. 2000 Oct 30 23 Philips Semiconductors Product specification Multiprotocol IC Card coupler TDA8006 handbook, full pagewidth CMDVCC VUP VCC I/O RSTIN CLK RST t0 t1 t2 t3 t4 t5 (= tact) ATR MGR235 Fig.11 Manual activation sequence using t3/t5. handbook, full pagewidth CMDVCC ATREN VUP VCC I/O CLK RST t0 t1 t2 t3 t5 (= tact) note1 ATR MGR236 (1) CLK = 45000 for version C1 or 40100 for versions C2 and C3. Fig.12 Automatic activation sequence. 2000 Oct 30 24 Philips Semiconductors Product specification Multiprotocol IC Card coupler Deactivation sequence When the session has completed, the microcontroller sets CMDVCC LOW (t10). The circuit then executes an automatic deactivation sequence: * Card reset (RST goes LOW) (t11) * Clock is stopped (t12) * I/O goes LOW (t13) * VCC falls to 0 V with typically 0.16 V/s slew rate (t14) * The step-up converter is stopped and CLK, RST, VCC and I/O become low impedance to GND (t15). TDA8006 t11 = t10 + 164T, t12 = t11 + 12T, t13 = t11 + T, t14 = t11 + 32T, t15 = t11 + 5T. tde is the time that VCC requires to fall to less than 0.3 V. handbook, full pagewidth CMDVCC RST CLK I/O VCC VUP t10 t11 t12 tde t13 t14 t15 MGR237 Fig.13 Deactivation sequence. Protection The main hardware fault conditions monitored by the circuit are: * Overcurrent on VCC * Short circuits between VCC and other contacts * Card take-off during transaction. When one of these problems is detected, the security logic block sets the OFF bit LOW which generates an interrupt warning the microcontroller and initiates an automatic deactivation of the contacts. When the deactivation has completed and CMDVCC has been set LOW, the OFF bit goes HIGH, unless the problem was caused by a card extraction, in which case it remains LOW until a card is inserted. 2000 Oct 30 25 Philips Semiconductors Product specification Multiprotocol IC Card coupler TDA8006 handbook,CMDVCC full pagewidth OFF RST CLK I/O VCC MGR238 Fig.14 Emergency deactivation sequence after VCC short circuited to ground. Auxiliary contacts C4 and C8 The auxiliary contacts C4 and C8 are controlled by ports P34 and P35 through two identical pseudo-bidirectional I/O lines. In the Idle state, port P34 is pulled HIGH to VDD by an integrated 20 k resistor and C4 is pulled HIGH to VCC by an integrated 10 k resistor. This allows operation with a VCC value of 3 V and a VDD value of 5 V. The first side on which a falling edge occurs becomes the master. An anti-latch circuit disables the detection of a falling edge on the other side, which becomes the slave. After a delay of approximately 200 ns (td), the N transistor on the slave side is turned on which transmits the `0' present on the master side. When the master side goes back to logic 1, the P transistor on the slave side is turned on during td, and then both sides return to their idle states. The maximum frequency on the I/O lines is 1 MHz. 2000 Oct 30 26 Philips Semiconductors Product specification Multiprotocol IC Card coupler LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDA VDDD Vn1 Vn2 In1 PARAMETER analog supply voltage digital supply voltage all input voltages except S1, S2 and VUP voltage on pins S1, S2 and VUP DC current into XTAL1, XTAL2, P30/RXD, P31/TXD, RESET, P33/INT1, P36/WR, P37/RD, P00 to P07, P20 to P27, P10/T2, P11/T2EX, EA, ALE, PSEN, CDELAY, PRES, INHIB, CLKOUT and TEST DC current from or to pins S1, S2 and VUP DC current from or to K0 to K3 DC current from or into pin ALARM (according to option choice) total power dissipation QFP44 QFP64 Tstg Tj Vesd storage temperature junction temperature electrostatic discharge on pins I/O, VCC RST, CLK, C4, C8 and PRES on other pins HANDLING see Table 12 Tamb = -20 to +85 C - - -55 - -6 400 500 +150 140 +6 CONDITIONS MIN. -0.5 -0.5 -0.5 -0.5 -5 TDA8006 MAX. +6.5 +6.5 +7.5 +5 V V V UNIT VDD + 0.5 V mA In3 In6 In7 Ptot -200 -5 -5 +200 +5 +5 mA mA mA mW mW C C kV -2 +2 kV Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) QFP64 QFP44 PARAMETER thermal resistance from junction to ambient CONDITIONS in free air 51 64 K/W K/W VALUE UNIT 2000 Oct 30 27 Philips Semiconductors Product specification Multiprotocol IC Card coupler TDA8006 CHARACTERISTICS VDD = 5 V; VSS = 0 V; Tamb = 25 C; for general purpose I/O ports refer to 80CE560 data sheet; unless otherwise specified. SYMBOL Supply VDDA VDDD IDD(pd) IDD(sm) analog supply voltage digital supply voltage supply current in power-down mode supply current in sleep mode VDD = 5 V; card inactive; note 1 4.2 4.2 - - - - - 6.0 6.0 250 1500 V V A A PARAMETER CONDITIONS MIN. TYP. MAX. UNIT card powered, microcontroller in - power-down mode but with clock stopped; note 1 130 IDD(om) supply current operating mode ICC = 65 mA; fxtal = 20 MHz; fclk = 10 MHz; fosc = 20 MHz; fCLKOUT = 20 MHz; 5 V card; notes 1 and 2 ICC = 65 mA; fxtal = 20 MHz; fclk = 10 MHz; fosc = 20 MHz; fCLKOUT = 20 MHz; 3 V card; notes 1 and 2 unloaded; fxtal = 20 MHz; fclk = 5 MHz; fosc = 10 MHz; fCLKOUT = 5 MHz; 5 V card; notes 1 and 2 unloaded; fxtal = 20 MHz; fclk = 5 MHz; fosc = 10 MHz; fCLKOUT = 5 MHz; 3 V card; notes 1 and 2 - 180 mA 65 - 90 mA 1 - 6 mA 0.5 - 4 mA Vth(VDD) threshold voltage on VDD (falling) threshold voltage on pin CDELAY voltage on pin CDELAY output current at pin CDELAY ALARM pulse width pin grounded (charge) VCDELAY = VDD (discharge) CCDELAY = 10 nF active LOW option; VOH = 5 V active LOW option; IOL = 2 mA active HIGH option; VOL = 0 V 3.6 50 - - - - - - -0.3 - - - 1.38 - -1 2 10 - - - 3.95 250 - VDD - - - 10 +0.4 -10 VDD + 0.3 V mV V V A mA ms A V A V Vhys(VthVDD) hysteresis on Vth(VDD) Vth(CDELAY) VCDELAY ICDELAY tW IOH VOL IOL VOH ALARM (open drain active HIGH or LOW output) HIGH-level output current LOW-level output voltage LOW-level output current HIGH-level output voltage active HIGH option; IOH = -2 mA VDD - 0.8 - 2000 Oct 30 28 Philips Semiconductors Product specification Multiprotocol IC Card coupler TDA8006 SYMBOL Crystal oscillator fxtal fext CLKOUT fCLKOUT VOL VOH to(r) to(f) fINT VVUP Vo(RST) Io(RST) VOL VOH tr tf Vo(CLK) Io(CLK) VOL VOH tr tf fCLK SR PARAMETER CONDITIONS MIN. TYP. - - MAX. UNIT crystal frequency frequency of external signal applied on pin XTAL1 4 0 25 25 MHz MHz frequency on pin CLKOUT LOW-level output voltage HIGH-level output voltage output rise time output fall time duty factor IOL = 5 mA IOH = -5 mA CL = 60 pF CL = 60 pF CL = 60 pF 0 - VDD - 1 - - 40 - - - - - - 2.5 6.5 - - - - - - - - - - - - 1.25 - - - 25 0.8 - 10 10 60 MHz V V ns ns % Step-up converter internal oscillation frequency voltage on pin VUP 2 - inactive mode; no load inactive mode; Io(RST) = 1 mA output current LOW-level output voltage HIGH-level output voltage rise time fall time when inactive and pin grounded IOL = 200 A IOH = -200 A CL = 30 pF CL = 30 pF inactive mode; no load inactive mode; Io(CLK) = 1 mA output current LOW-level output voltage HIGH-level output voltage rise time fall time clock frequency duty factor slew rate (rise and fall) when inactive and pin grounded IOL = 200 A IOH = -200 A CL = 30 pF CL = 30 pF 1.25 MHz idle configuration operational CL = 30 pF CL = 30 pF 0 0 0 0 - - 0 0 0 0 - - 1 0 45 0.2 3 - 0.1 0.3 -1 0.3 VCC 0.1 0.1 MHz V Reset output to the card (pin RST) output voltage V V mA V V s s V V mA V V ns ns MHz MHz % V/ns VCC - 0.7 - Clock output to the card (pin CLK) output voltage 0.1 0.3 -1 0.3 VCC 8 8 1.5 10 55 - VCC - 0.5 - 2000 Oct 30 29 Philips Semiconductors Product specification Multiprotocol IC Card coupler TDA8006 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Card supply voltage (pin VCC); note 3 VO(VCC) card supply output voltage inactive no load IO(VCC) = 1 mA pin grounded active ICC < 65 mA; 5 V card ICC < 65 mA; 3 V card current pulses of 40 nAs with ICC < 200 mA; t < 400 ns; f < 20 MHz; 5 V card current pulses of 24 nAs with ICC < 200 mA; t < 400 ns; f < 20 MHz; 3 V card IO(VCC) ICC(sd) SR card supply output current shutdown current at pin VCC slew rate up or down (capacitor = 100 to 300 nF) from 0 to 3 or 5 V VCC short circuited to GND 4.75 2.8 4.6 5 3 - 5.25 3.2 5.4 V V V 0 0 0 - - - 0.1 0.3 -1 V V mA 2.75 - 3.25 V - - - 0.10 - - -80 0.16 65 250 - 0.30 mA mA mA V/s Data line (pin I/O); note 4 Vo(I/O) output voltage inactive no load Io(I/O) = 1 mA Io(I/O) VOL VOH VIL VIH IIL ILIH ti(r) ti(f) to(r) to(f) Rpu(int) output current LOW-level output voltage HIGH-level output voltage LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input leakage current input rise time input fall time output rise time output fall time internal pull-up resistance between I/O and VCC inactive and pin grounded I/O configured as output; IOL = 1 mA I/O configured as output; IOH < -50 A I/O configured as input I/O configured as input VIL = 0 V VIH = VCC CL = 30 pF CL = 30 pF CL = 30 pF CL = 30 pF 0 - 0 0 0.8VCC -0.3 1.5 - - - - - - 8 - - - - - - - - - - - - - 10 0.1 0.3 -1 0.3 V V mA V VCC + 0.25 V +0.8 VCC -600 20 1 1 0.1 0.1 13 V V A A s s s s k 2000 Oct 30 30 Philips Semiconductors Product specification Multiprotocol IC Card coupler TDA8006 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Auxiliary card contacts (C4 and C8); note 5 Vo(C4,C8) output voltage inactive no load Io(C4,C8) = 1 mA Io(C4,C8) VOL VOH VIL VIH IIL ILIH ti(r) ti(f) to(r) to(f) td Rpu(int) output current LOW-level output voltage HIGH-level output voltage LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input leakage current input rise time input fall time output rise time output fall time delay between falling edge on P34 and C4 (or C4 and P34) internal pull-up resistance between C4 and VCC and C8 and VCC maximum frequency on C4 or C8 inactive and pin grounded C4 or C8 configured as output; IOL = 1 mA C4 or C8 and I/O configured as output; IOH < -50 A C4 or C8 configured as input C4 or C8 configured as input VIL = 0 V VIH = VCC CL = 30 pF CL = 30 pF CL = 30 pF CL = 30 pF 0 - - 0 0.8VCC -0.3 1.5 - - - - - - - 8 - - - - - - - - - - - - - - 10 0.1 0.3 -1 0.3 V V mA V VCC + 0.25 V +0.8 VCC -600 20 1 1 0.1 0.1 200 13 V V A A s s s s ns k f(max) Timing tact tde t3(start) t5(end) - - 1 MHz activation sequence duration deactivation sequence duration start of the window for sending clock to the card end of the window for sending clock to the card - - - 145 - - - - 225 100 130 - s s s s Output ports from extension (K0 to K3) VOL VOH LOW-level output voltage HIGH-level output voltage IOL = 2 mA IOH = -2 mA - VDD - 1 - - 0.4 - V V 2000 Oct 30 31 Philips Semiconductors Product specification Multiprotocol IC Card coupler TDA8006 SYMBOL PARAMETER CONDITIONS - MIN. TYP. - - - - MAX. UNIT Card presence input (pin PRES) VIL VIH ILIL ILIH Notes 1. IDD in all configurations include the current at pins VDD, VDDA and VDDRAM. 2. Values given for program executed from internal ROM. Current consumption may be higher if program is executed from external ROM or if charges are present on I/O ports. 3. A ceramic multilayer capacitor having a minimum value of 100 nF with a low ESR should be used to obtain these specifications. 4. The I/O line has an integrated 10 k pull-up resistor at pin VCC. 5. Pins C4 and C8 have integrated 10 k pull-up resistors at pin VCC; ports P34 and P35 have integrated 20 k pull-up resistors at pin VDD. OPTIONS Table 12 Options FEATURES Alarm Presence MOVEC protection active HIGH active HIGH on OPTIONS active LOW active LOW off LOW-level input voltage HIGH-level input voltage LOW-level input leakage current HIGH-level input leakage current Vi = 0 V Vi = VDD 0.3VDD - 20 20 V V A A 0.7VDD - - 2000 Oct 30 32 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2000 Oct 30 VDD +5 V 2 J1 C20 100 nF GND 1 J1 ALARM C21 33 F C7 4.7 nF CLKOUT CDELAY R1 PRES GND VDD VCC I/O C8 C4 C5 100 nF VUP S2 VDDA S1 AGND CLK RST GNDRAM VDDRAM n.c. n.c. K1 VDD K2 C6 100 nF C10 47 pF CARD READ UNIT C1 100 nF C4 100 nF 0 VDD C9 100 nF C14 100 nF R2 100 k 33 reset RESET P10/T2 P11/T2EX n.c. RX TX P30/RXD P31/TXD P33/INT1 P36/WR P37/RD P20 P21 34 35 36 37 38 39 40 41 42 43 44 1 P22 2 P23 3 PSEN 4 ALE 5 XTAL2 6 XTAL1 7 EA 8 P03 9 P02 10 P01 11 P00 TEST 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 APPLICATION INFORMATION Philips Semiconductors handbook, full pagewidth Multiprotocol IC Card coupler VDD VDD C8 C7 C6 C4 C3 C2 C1 C5I C6I C7I C8I C2 100 nF C3 10 F C5 C1I C2I C3I C4I 33 TDA8006AH 17 16 15 14 13 12 Y2 C21 33 pF 14.745 MHz MGR239 C20 33 pF Product specification TDA8006 Fig.15 Application diagram. Philips Semiconductors Product specification Multiprotocol IC Card coupler PACKAGE OUTLINES QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm TDA8006 SOT319-2 c y X 51 52 33 32 ZE A e E HE A A2 A1 (A 3) Lp bp 64 1 wM D HD ZD B vM B 19 vMA 20 detail X L pin 1 index wM e bp 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.20 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.50 0.35 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 1 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 7 0o o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT319-2 REFERENCES IEC JEDEC MO-112 EIAJ EUROPEAN PROJECTION ISSUE DATE 97-08-01 99-12-27 2000 Oct 30 34 Philips Semiconductors Product specification Multiprotocol IC Card coupler TDA8006 QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2 c y X A 33 34 23 22 ZE e E HE wM bp pin 1 index 44 1 bp D HD wM 11 ZD B vM B vMA 12 detail X A A2 (A 3) Lp L A1 e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.10 A1 0.25 0.05 A2 1.85 1.65 A3 0.25 bp 0.40 0.20 c 0.25 0.14 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD 12.9 12.3 HE 12.9 12.3 L 1.3 Lp 0.95 0.55 v 0.15 w 0.15 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 10 0o o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT307-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 97-08-01 2000 Oct 30 35 Philips Semiconductors Product specification Multiprotocol IC Card coupler SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: TDA8006 * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 2000 Oct 30 36 Philips Semiconductors Product specification Multiprotocol IC Card coupler Suitability of surface mount IC packages for wave and reflow soldering methods TDA8006 SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable 2000 Oct 30 37 Philips Semiconductors Product specification Multiprotocol IC Card coupler DATA SHEET STATUS DATA SHEET STATUS Objective specification PRODUCT STATUS Development DEFINITIONS (1) TDA8006 This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Preliminary specification Qualification Product specification Production Note 1. Please consult the most recently issued data sheet before initiating or completing a design. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2000 Oct 30 38 Philips Semiconductors Product specification Multiprotocol IC Card coupler NOTES TDA8006 2000 Oct 30 39 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2451, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260, Tel. +66 2 361 7910, Fax. +66 2 398 3447 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 3341 299, Fax.+381 11 3342 553 For all other countries apply to: Philips Semiconductors, Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000 Internet: http://www.semiconductors.philips.com SCA 70 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753504/04/pp40 Date of release: 2000 Oct 30 Document order number: 9397 750 07622 |
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